15 December 2017

Deja Vu All Over Again, part the second

As regular reader may remember, I've told the tale of my eclectic journey through the data worlds. One of those legs involved an ancient (even at the time I used it in the late 80s) TI-990 based VAR software for the construction industry. Even more odd, this company also had a side-line business in mechanical contracting parts, aka plumbing, which ran an application on a separate machine run by TI's then single chip version of that same 990. The contracting software vendor is defunct, while the wholesale application kind of still exists; the company's been bought and the software converted to normal chips and languages. I eventually migrated the company to (again) two applications running on an RS-6000/AIX and Progress. Since Progress wasn't/isn't especially relational while its 4GL is COBOL/BASIC-ish, and thus schemas were subordinate to code, integration wasn't as simple as falling off a log, but it worked. And last I talked with the folks, still running.

So, what has all of that got to do with today, you might ask? As well you might. Well, here's some of the news.
There are dozens of companies experimenting with ISC and early results look quite promising: offloading select tasks from CPU to SSDs can reduce latencies by a factor of 2-3 while also decreasing power consumption. The key purpose of ISC is to reduce (or even avoid) "expensive" data transfers from a storage device to a processor by performing computing operations on the former. Latency reductions will be crucial in the looming 5G era, especially for edge computing environments.

So, we have non-volatile DIMMs (somewhere, sometime in the future) and now a CPU that talks to SSD/foo skipping memory altogether. And that's not sort of new.

Here's the point of the 990 (from the Wiki):
The TI-990 had a unique concept that registers are stored in memory and are referred to through a hard register called the Workspace Pointer. The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU. This meant that it didn't matter if the "registers" were real registers in the CPU or represented in memory. When the Workspace Pointer is loaded with a memory address, that address is the origin of the "registers".

There are three hard registers in the 990; the Workspace Pointer (WP), the Program Counter (PC) and the Status register (ST). A context switch entailed the saving and restoring of only the hard registers.

The reason this even made sense was that, in the 70s and 80s when the machine was in wide use, CPU and memory ran about the speed, so skip the middle man. It was a very successful machine among VARs for quite a while. But, as one might suspect, when chips and memory progressed to the point where load/store RISC architectures took off, the 990 was doomed. But the idea of compact circuitry talking directly to its data is not such a bad one. Back to the future?

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